The graphic interface and the settings of your pc could be different from the ones taken back here. For this reason you refer to the manual of your mother card for greater information and specific settings. flash bios

S2K Bus Driving Strenght [Auto/Manual]

This option is present on the motherboard with chipset AMD and Socket A. S2K is the bus of the cpu AMD Athlon; it can control the signals of the bus. We suggest to leave the setting on Auto and to change it only if you want to make an overclock. flash bios

DRAM TIMING [BY SPD/OPTIMAL/SPD/YES/Manual]

Alternative name: Configure Sdram By SPD, DRAM TIMING SELECTABLE, MEMORY DETECT BY, MEMORY TIMING, SDRAM CONFIGURATION, SDRAM CONTROLLED BY.

With this setting you can change the access time of system memory. flash bios

CPU: DRAM CLOCK RATIO [Auto, Default]

Alternative name: DRAM FREQUENCY, FSB RATIO, CPU RATIO

This value sets the frequency access between CPU and system memory. flash bios

DRAM CLOCK [Auto, BY SPD, SPD]

Alternative name: DRAM FREQUENCY, MEMORY FREQUENCY

This value sets the access time to DDR system memory.

Video Memory Cache Mode [USWC/UC]

This option can accelerate the transfer of dates between cpu and video memory. flash bios

Bank 0/1, 2/3, 4/5 DRAM Timing [8-10ns/Normal/Medium/Fast/Turbo/Back to 10 ns]

This setting regulates the timing on the access to the memory. A very pushed timing, united to the other settings of performance of the memory, involves a remarkable increase in demanding performances in the applicatory ones most, but if the memory is not of excellent quality the system can become extremely unsettled. It is possible to try the settings leaving from that several bass. If the system becomes unsettled it is possible to increase the tension lightly by I/O, if the mother card allows it. Applying the same setting for every desk of memory is advisable in any case. It is not possible to pretend resulted convincing from desks of memory of low quality. flash bios

DRAM Bank Interleave [Disabled/2-Way/4-Way]

This setting, joined to the other settaggi on the performance of the memory, involves a remarkable increase in the demanding performances in the applicatory ones most. It is not possible to pretend resulted convincing from desks of memory of low quality. The setting several performante is the interleave in '4-Way'.

Delay DRAM Read Latch [Auto/No delay/0.5ns/1.0ns/1.5ns]

This setting regulates the delay after which the elements can be read of, put also on various desks. With an only desk of memory of good quality setting up a null delay definitely improving the performances together to all the other settings on the timing of the memory is possible. Leaving the setting on the predefinito value if the memory is put on more than one desk, and above all if the same ones is not perfectly identical is advisable. Every memory lightly has some cycles of working unusuals one from the other: this introducing a delay to be able to synchronize the transfer of the data makes necessary. flash bios

MD Driving Strenght [HI/Lo]

This setting regulates the intensity of the signal between the given for the memory chipset and the bus. It is possible to leave on 'Hi' to reduce the immunity to the troubles, making the pc stabler. If set up on one will have a reduction of the consumption of quite insignificant current.

SDRAM Cycle Lengh o CAS Latency [3/2/1]

This is the most important setting which affects the performances of the memory. Shows how many cycles of clock the system awaits to go to read the datum in memory. Most memories in commerce firmly hold the CAS Latency (delay Column Address Strobe) set up to 2. Attention: a too short wait could not assure the stability of the datum and make the pc estremamemte unsettled. If the system allows it, it is possible to raise the I/O tension lightly to improve the reliability. It is not possible to pretend resulted convincing from memory desks of low quality or not recent production. If high performances are wanted from the memory, using an only desk is advisable. If the amount of RAM should not be sufficient, putting beside identical memory forms the most possible is advisable. This because every memory lightly has some cycles of working unusuals one to other, and to synchronize the transfer data inserting a period late (DRAM Read Latch) is necessary. flash bios

Memory Hole [Disabled/15-16M]

This setting reserves the suitable memory space for particular types of peripherals which require 1 mbs of free memora beneath the 16 mbs. Deactivate this option if it is not at all necessary.

PCI Master Pipeline Req [Enabled/Disabled]

This setting enables the requests for queueing for the interruptions of the devices on the PCI (Peripheral Component Interconnect) bus. This way the dispute of the bus will be a greater available band reduced by several peripherals, laciando for the single transactions. To exploit this mode, every single peripheral must be corresponding to the specifications PCI Compliant 2.1. If they do not have problems is advisable leaving the setting on the predefinito value, since they could not improve according to the type of the data to move the performances.

P2C/C2P Concurrency [Enabled/Disabled]

This setting checks the operations of agreement for the transactions PCI-TO-CPU and CPU-TO-PCI. If activated he reduces the dispute for the possession of the bus, however the peripherals must be compatible with the specifications PCI Compliant 2.1. If they do not have problems leaving the setting on the predefinito value is advisable. flash bios

Fast R-W Turn Around [Enabled/Disabled]

This setting activates or deactivates a timing rapids of the cycles of lettura-scrittura. If memories of low quality are used or a system bus specifies outside deactivating this mode, not to have problems of instability of the system is advisable. Activating it with memories to high performance is possible. It is not possible to pretend resulted convincing from desks of memory of low quality.

System BIOS Cacheable [Enabled/Disabled]

This option allows to keep in the memory L2 cache the activities of the BIOS. This way the access will be more immediate but it is possible to have a prestazionale loss in some applicatory in which the multimedia instructions of the processor are heavily exploited. flash bios

Video RAM Cacheable [Enabled/Disabled]

When this option is activated, the cache of L2 second level is used to improve the performances to the access of the display memory. Even though please can draw a light increase of the performances to the opening of the applcazioni, activating this function in order to avoid incompatibility problems is unadvisable. Not all of the cards support this option.

AGP Aperture size [4/8/16/32/64/128/256]

The AGP mode is deactivated if set up a value lower than 32 mbs. If a value equal or higher than the half of the amount of the memory RAM of system is set up the performances do not increase and in certain cases they decrease and create problems to the system of addressing of the memory of the operating system.

AGP 4x Mode [Enabled/Disabled]

This option activates the AGP-4x support for the graphic cards which support this transfer mode data. Activating this mode in most cases the performances will not increase in perceptible way and in a large number of cases the setting will not be adequately used by the operatico system with consequent blocks and/or remarkable instability of the system. Not activating this option if the system bus is (system overclock) out specification, the performances can decay is advisable. flash bios

AGP Driving Control [Auto/Manual]

This option specifies if the control of the feeding of chip designer must be automatic or manual. In the second case inserting a value of the tension expressed by a hexadecimal number to two digits is possible. Since a linear correspondence does not exist between the inserted value and the tension of graphic pilotage of the core, inserting some values at random is absolutely not recommended. If some problems owed to the value of the feeding presumedly are identified not correct, gathering information on the site of the producer of the graphic card to control it is possible the parameters of working and then occore were optimized manually modify the option. flash bios

Fast Write Support [Enabled/Disabled]

This option sets up the mode of fast writing for the transactions on the AGP Bus. If he registers her graphic he supports this function, the Fast Write can be activated, with very little improvement of the performances 3 d. In certain cases problems of incompatibility or instability of the system can rise and it could be necessary deactivate this option. Do not activate this option if the system bus is out specification, the performances can decay.

K7 CLK_CTL [Default/Optimal]

This option regulates the parameters of working of the processor and was removed from the available voices in the next updatings of the BIOS for mother many cards. This because if set up 'defaults' could rise up problems apparently inexplicable. If it should be present, please always set up it on 'Optimal'.

CPU to PCI Write Buffer [Enabled/Disabled]

When this option it is activated, the processor can consecutively write on the PCI Thin Bus to four words of data, reducing the times of condivisione of the bus. The cycles of wait of the processor are reduced this way, with a general improvement of the performances. However, if the PCI Bus lodges very old peripherals, the writing buffer could create some blocks it or instability for which should be deactivated. flash bios

PCI Dynamic Bursting [Enabled/Disabled]

This option, if activated, he improves the working of the CPU-to-PCI Write Buffer, identifying what transactions can be tried and what cannot be stored in the buffer. This avoids the filling and the emptying of the buffer if the transaction does not support the Write Buffer. Useless time waste are avoided this way.

PCI Master 0 WS Write [Enabled/Disabled]

This option, if activated, the writing of the data imposes on the PCI Bus without wait states (Wait state), improving the performances. Some peripherals as economic acquisition cards could not support this function

PCI Delay Transaction [Enabled/Disabled]

This option extends the support to the specifications 'PCI compliant 2.1' which foresee the possibilià to make transactions late thanks to the Write Buffer. flash bios

PCI#2 Access #1 Retry [Enabled/Disabled]

This option, if activated, the access of the AGP Bus On The PCI Bus imposes in mode limited in the time, allowing the other peripherals to dialogue with all the system.

AGP Master 1 Ws Write [Enabled/Disabled]

This option, if deactivated, introduces 2 cycles of clock late in the execution of the writing of the data on the AGP Bus, assuring a greater stability. If the setting is activated, an only cycle of clock will be executed late, obtaining an imperceptible improvement in the applications 3 d. We remind that the performances can be improved, to technology equality, to discapito of the stability.

AGP Master 1 Ws Read [Enabled/Disabled]

This option, if deactivated, introduces 2 cycles of clock late in the execution of the reading of the data on the AGP Bus, assuring a greater stability. If the setting is activated, an only cycle of clock will be executed late, obtaining an imperceptible improvement in the applications 3 d. We remind that the performances can be improved, to technology equality, to discapito of the stability. flash bios

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